Currently in electronics circuit design, there is a trend towards miniaturization, specifically, towards the thinning of the oxide layer that forms the insulator between the gate-electrode and the channel in a MOS transistor. As a result of this thinning, the voltages supportable at the gate-electrode, as well as the gate-to-source voltage and the drain-to-source voltage become smaller. Lower voltage and thinner gate oxide are both concomitant with lower power consumption and higher switching speeds. However, when an inevitable anomalous high voltage spike happens, which can occur due to an impedance mismatch, an inductive coupling with a higher voltage line, or due to the need to support legacy protocols that used thicker gate-oxides and higher voltages, then the thin-oxide gate will breakdown and result in circuit failure. Therefore, there is need for a mechanism to protect a circuit from high-voltage spikes, and for such mechanism to be constructed out of thin-oxide transistors. The thin-oxide refers to gate-oxide tolerable of 1.8V across it and thick oxide is referred as gate-oxide tolerable of 3.3V across it.
Hence, it is desirable to have a thin-oxide current clamp that prevents excessive current draw due to the anomalous high voltage condition.